FPGA Engineer ===NGM(傳輸系統(tǒng)部門)

Key Responsibilities:

lParticipate in outlining product architecture definition and derive the low level FPGA specification.

lControl the logic design including component selection, pin definition, architecture, simulation, synthesis, place&route, debugging on board.

lCooperate with category managers, suppliers and other relevant functions to solve technical issues for quality.

Job Requirement:

l3+ years experience in FPGA design.

lComplete understanding of the FPGA design flow.

lDesign background in OTN,PDH, SDH,WDM or packet based telecommunication equipment

lExperience with simulation, verification on board.

lDesign experience of Data forwarding engine or Traffic Manager is a plus.

lKnowledge of development of board level circuit and embedded SW.

lKnowledge of Micro-processors and network processors environments

Senior FPGA design engineer==WCDMA-RA(3G事業(yè)部）

Job Description:

lParticipate in outlining product architecture definition and derive the low level FPGA specification.

lControl the logic design including component selection, pin definition, architecture, simulation, synthesis, place&route, debugging on board.

lCooperate with category managers, suppliers and other relevant functions to solve technical issues for quality.

Job Requirements:

l3+ years experience in FPGA design.

lComplete understanding of the FPGA design flow.

lDesign background in telecommunication equipment

lExperience with simulation, verification on board.

lDesign experience of Data forwarding engine or Traffic Manager is a plus.

lKnowledge of development of board level circuit and embedded SW.

lKnowledge of Micro-processors and network processors environments

lBachelor/Master of Science (Electrical Engineering)

lFluent English in both speaking and writing

MWR R&D - FPGA Design Senior Engineer
--MWR R&D (微波無線研發(fā)事業(yè)部）

Key Responsibilities:

l Participate in outlining product architecture definition and derive the functional specification for FPGA functionality level.

l Work as the technical point of contact on the FPGA area.

Job Requirements:

l Be able to generate block level definitions and FPGA requirements for the design team

l Complete understanding of the FPGA design flow.

l Knowledge of FPGA-Design and Formal Verification tools. Good VHDL experience

l With TDM or Packet based FPGA design experience more than 2 years.

Education/Skills:

l Bachelor/Master of Science (Electrical Engineering)

l >5 years working experience in the related area

l Fluent English in both speaking and writing

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MWR R&D - FPGA Design Engineer

Key Responsibilities:

l Detailed logic functionality and FPGA code design/implementation.

l Simulating the needed functionality

l Generating the test bench environment for the verification

l FPGA verification planning, validation and testing on board.

l System emulation and bring-up on FPGA prototype

Job Requirements:

l Knowledge of FPGA-Design and Formal Verification tools. Good VHDL (or Verilog) RTL experience

l Good knowledge of Altera or Xilinx FPGA is an advantage

l Block level Micro-architecture, RTL Design, Verification, Synthesis and timing.

l Excellent analysis/debugging skills and using scripting languages (e.g. HiT, TCL)

Education/Skills:

l Bachelor/Master of Science (Electrical Engineering)

l >2 years working experience in the related area

l Fluent English in both speaking and writing

MWR R&D - FPGA
Verification Specialist

Key Responsibilities:

·
Participate in outlining FPGA concept and architecture definition and derive the System-on-Chip functional and design specification for FPGA functionality level.

·
Preparation and review of functional and design specification for FPGA

·
Verify logic functionality and FPGA code design/implementation.

·
Verification and simulation of of needed functionality on block level

·
System emulation and bring-up on FPGA prototype

·
Ensure effective testing and high quality product delivery by advanced FPGA verification planning, validation and testing on board.

·
Support HW/SW Bring-up and debug

·
Cooperate with system engineers, HW/SW development, suppliers and other relevant functions to solve technical issues for quality

Job Requirements:

·
3+ years of FPGA/ASIC verification experience in the R&D of Telecommunication Networks or Communication industry.

·
Excellent VHDL/Verilog know-how and many years of coding and modeling experience

·
Complete understanding of the FPGA/ASIC design flow and process.

·
Knowledge of FPGA/ASIC design and verification tools.

·
A strong background in TDM and Packet (IP/Ethernet) based telecommunication network solution

·
Comprehensive knowledge in the field of Carrier Ethernet (Ethernet switch etc)

·
Microwave radio transport and related telecommunication network solution knowhow

·Detailed understanding of SDH and PDH technology and interfaces

·
Knowledge of the diverse controller, power and timing solutions for different telecommunication applications

Education/Skills:

·
Bachelor/Master of Science (Electrical Engineering)

·
>3 years working experience in the related area

·
Fluent English in both speaking and writing